How to build Two clocks coming out from a mux. One is high frequency, other is low

[Vivek Rajeev]

Mux A and B pin has two clocks.
A is high frequency
B low frequency
How do you build clock from mux output.
What constraints you need to apply on the mux pins

Thanks

 

[shalin mandiwala]

Can you clarify what do you want to generate? Mux is to select either A or B input.So, you will get either High or Low frequency clock based on selection line.

 

[CataM]

If you want to build clock with other frequency that you already have, it can be done with T flip-flop.

 

[dpaul]

My guess, this is what comes to my mind in a flash......

Considering the right-hand side of the MUX you have only 1 clock domain.
But considering the left hand side too, you have two different clock domains for the entire design.

In my opinion you may try out with two constraints files. In one file the high freq clk can be set to have false path and in the other the low freq clk can be set to have false path.

 

[morris_mano]

Is your question related to timing analysis ? what do you mean by how to build a clock?
In SDC, you can define both mux input as a clock with their respective frequency. Then you have to run STA twice using "set_case_analysis 0 mux_sel" once and second using "set_case_analysis 1 mux_sel" to ensure your design is timing closed for both clock frequency.

 

[vGoodtimes]

The hidden factor here is the select line. The select line must meet setup/hold at least based on min pulse time. basically, the select cannot be allowed to change when a clock is currently low/high and about to transition to high/low. when the clocks are synchronized, this is possible. when not, different circuits are used to ensure a clean transition.

 

[andre_luis]

If I understood correctly the problem statement, the dpaul's approach seems as being the more reliable: For this task could be used 2 MUXes, each one having just one of these two clocks, leaving the 2nd input of boths as unused. The selector pins should be necessarily synchronized with one of these two clocks in order to provide the necessary switching time.

 

[dpaul]

As I had mentioned earlier, I had just replied to this post initially without giving it a very deep thought.

The selector pins should be necessarily synchronized with one of these two clocks in order to provide the necessary switching time

.
I think the above should be considered.
But I don't have any experience in designing/analyzing clock generation/control circuitry. There should be documents out there on how to do this.

But the problem is the OP has provided very less info on the practical use case and then is silent.

 

[morris_mano]

Usually glitch free clock muxes are used to mux two clocks provided both clocks are present when clocks are being switched.

 

[ads-ee]

But the problem is the OP has provided very less info on the practical use case and then is silent.

Which is why I selectively answer vague questions and usually don't if the OP ask a vague question and has no track record of returning to the site to see if anyone answered.

The majority of these type of posts are fly-by posts at multiple forums and if they get an answer on another forum they never come back to the other forums to let anyone know the problem was solved and how. I've even found these posters asking the same questions with the same spelling/syntax errors on other forums in many cases.