Can any one suggest me about who to proceed with IO pad cell design...
As it has large transistors of huge width and ESD protection cicuitry,, can any one help me in telling what actually inside it and how to proceed with layout of such circuitry...
Can you give more detail? What are you trying to do? If you are doing digital stuff, pads cells are usuallly part of the library along with the standard cells. If you are doing analog, then please give some basic info about speed, voltage, output current,etc.
As for ESD your layout design rules will have a section on how to lay out output devices to protect them from ESD.