u24c02
Advanced Member level 1
Now I'm trying to study about time borrow as refer to here:
http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html
Especially, I'm looking at this:
How to get time and how to get this not setup violation?
In my understanding, L1 to L2 needed 8ns time but the period is 5ns. Then it needs 3ns more. But L2 capture the data of L1 at PH2 positive sensitive clock. At this time, the data have not arrived yet (it needed 3ns).
I can't understand how to say this is not setup violation L1 to L4?
http://www.vlsi-expert.com/2011/03/static-timing-analysis-sta-basic-part2.html
Especially, I'm looking at this:
How to get time and how to get this not setup violation?
In my understanding, L1 to L2 needed 8ns time but the period is 5ns. Then it needs 3ns more. But L2 capture the data of L1 at PH2 positive sensitive clock. At this time, the data have not arrived yet (it needed 3ns).
I can't understand how to say this is not setup violation L1 to L4?