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how to bidirectional signal in xilinx EDK tool ???

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Member level 4
Nov 28, 2002
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xilinx iobuf

i am facing a problem with EDK tool. can you please assist me in this
regard.the problem is .

i am using a top file of name npdmm.vhd, which using a INOUT signal.when
i synthesis using EDK tool , a npdmm_wrapper file is creating by EDK
tool which describes the npdmmA inout signal into three signal like npdmmA
_O, npdmmA _I , and npdmmA _T .when i modifing the wrapper file as per my
desire logic and synthesising it once again , it overwrites the
modified wrapper file and unable to synthesis further.

The error messages are the following:

ERROR:Xst:2585 - Port <npdmmA_I> of instance <npdmm> does not exist in
definition <npdmm>.
ERROR:Xst:2585 - Port <npdmmA_O> of instance <npdmm> does not exist in
definition <npdmm>.
ERROR:Xst:2585 - Port <npdmmA_T> of instance <mpdmm> does not exist in
definition <npdmm>.

I would be pleased to know how to handle the bidirectional signal in
EDK tool.

iobuf xilinx

I am not sure how you define the INOUT in yout wrapper.

inout_i: IOBUF port map
( O => out, IO => inout , I => in, T => t );

post ur top level file here?

edk error:xst:2585 port


also search on and


xilinx edk buffer

The way you handle bidirectional signals is handled the same way in the EDA kit as in anyother instance. You need to make sure you have the code for the signal(s) properly spec'd in the code. It sounds like you have not tied two sets of code together properly via internal signals.

Here is an example of the code you can use

-- IOBUF : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the architecture body of the design code. The
-- declaration : instance name (IOBUF_inst) and/or the port declarations
-- code : after the "=>" assignment maybe changed to properly
-- : connect this function to the design. Delete or comment
-- : out inputs/outs that are not necessary.

-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.

-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.

Library UNISIM;
use UNISIM.vcomponents.all;

-- <-----Cut code below this line and paste into the architecture body---->

-- IOBUF: Single-ended Bi-directional Buffer
-- All devices
-- Xilinx HDL Language Template version 8.2.2i

generic map (
DRIVE => 12,
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
port map (
O => O, -- Buffer output
IO => IO, -- Buffer inout port (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input

-- End of IOBUF_inst instantiation


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