How to avoid short violations in SoC encounter?

[srinivasank]

Hi friends

iam working on soc encounter
iam designing a digital ASIC
After my place of standard cells and trial routing, i get close to 600 short violations
Can someone tell me how to avoid short violations

 

[kumar_eee]

short violations

What kind of shorts they are?. Signal nets or Power Nets?.

 

[srinivasank]

Re: short violations

hi kumar

I have just put up the screen shot of it

It says "Regular via of Net PLE_IN & Blockage of cell in3, layer M2 =...."

 

[kumar_eee]

short violations

Do you have any routing blockage?. I think its something with routing blockage.

 

[srinivasank]

Re: short violations

I have not put any routing blockage or placement blockage

Then where is the violation between the wire and cell blockage coming from

 

[itsmeteja]

Re: short violations

Case i ::
You might have cell internal geometries, in PnR tool it might have been modeled as routing blockage internal to the cell to indicate the PnR tool to do routing accordingly.

Open the gdsii/oasis/laff of the cell and confirm that there are geometries are present and you can edit/remove the blockages internal to the cell

case ii::
There might be cell pin access point is not modelled by PnR tool properly.