jjww110,
this is not possible in this scenario. At any instant of time, both clocks are in opposite states to each other.
This kind of situation is very common in designs where u have to select either CLK or its invert based on some signal.
My question is , how do u switch such that there is no glitch ??
hi,abhishek_elec
sorry,i have not noticed the relation between two clocks,under this situation, i think this is not a good design and may change design to avoid it ,what's your comment?
jjww110,
the requirement is to switch the clock at the run time. It;s not a static selection of clock. So while designing u can't determine which flops will clock at neg-egde and which at pos-edge.
I even discussed this topic. You can find it by searching "clock mux" this kind of key words. In this topic, you can also watch the related circuit for your reference.