How to avoid clock,signal and reset violations when doing scan insertion?

[S.Nikhil]

Hi everyone!

While attempting to do scan insertion for a desig, I am finding many uncontrollable clock and uncontrollable asyncrhonous signals like set and reset violations.

Can anyone guide me on how to avoid these violations?

Can anyone send me the necessary commands to perform autofix in xg mode.

Thanks
Nikhil

 

[varkylin]

Scan Insertion

hi you can use the signal of Test Mode to fix the set and reset signal . when have hold violation,you can use transparent latch .

 

[lakshman.ar]

Scan Insertion

uncontrollable clocks are those which come out frm a combo logic ( dividers ..etc)
when doin DFT, all the controls of the FF must be wrt to the TEST EN signal,
in the sense once if TEST EN =1, then automatically the entire ship should be in scan mode .... for this all the clock of the FF should be controllable externally ( at pin level)

werver u get a "uncontrollable clk" or , pls do the following
1) MUX the functional CLK with the "test clk" with the TEST EN as the select line and then givethe o/p of mux as the input to the FF ( so that wen TEST EN =1, the test clk will be given to all the FF and wen TEST EN=0, the chip functions with normal clock )

pls lemme kno, if u hv ne concerns

WBR
Lakshman

 

[raul_777_h]

Scan Insertion

You can use autofix feature of DFT compile to fix uncontrollable case.

 

[mohaddin]

Scan Insertion

Hi

Good man

Lucky me

Regards

Mohi baba