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How to automatically convert a Verilog code to a GDS2 file?

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Hi everyone.
I have designed an ASIC multiplier and written its descriptive verilog code. Now, I want to extract its layout automatically (a gds2 file) from the verilog file. It will be kind of you guide me through your worthy explanations or useful documents or videos.
Thank you in advance.

Google "RTL2GDS flow". For example,

You cannot extract a gds2 from a verilog file because verilog does not carry any physical information or implementation guidelines. There are literally dozens of steps to take a verilog RTL through logic synthesis and physical synthesis before you get a gds file. Tutorials are available online.

A truly automatic flow is somewhat of a myth.

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