How to analyze Vout / Vin in S/H circuit ?

[mpig09]

Dear all :

The attached file has two sample and hold circuit,
I try to analyze the Vout / Vin, but the result always
Vout / Vin =1.

Could you help me how to analyze the circuit ?

 

[MikeR]

What parameter you want analysis? And what model of opamp you use?
For begining you can add input votage offset and changing sampling frequency. And what about pedestal error?

 

[hr_rezaee]

Hi
edited see below
regards

 

[mpig09]

Dear all :

First circuit : C0=C5=1.2p
C1=C3=0.8p

Second circuit : C1=C2=1.2p
C0=C3=0.8p

Could anyone describe how to analyze ?
(analyze principle / formula)

Thanks for your kindly help.

mpig

 

[hr_rezaee]

Hi
sorry
I took a mistake.

draw half model of fully diff S/H.
charges in sampleing phase:
Q0=Vcm.C0
Q1=Vin.C1

charges in holding phase:
Qout=Q0+Q1=Vcm.C0+Vin.C1
Vout = (Vcm.C0+Vin.C1)/C0 = C1.Vin/C0+Vcm

VOdiff=C1.VINdiff/C0
C1=1.2p, C0=0.8p
VOdiff=1.5 VINdiff

regards

 

[mpig09]

Dear hr_rezaee :

For second circuit :
Sample phase
Q0=Vin*C0, Q1=DAC*C1

Hold phase
Vout=Vin + Qout / C0
Qout=Q0+Q1
so, Vout=Vin+ (Vin*C0+DAC*C1) / C0
=Vin + Vin + DAC*(C1/C0)
=2*Vin + DAC*(C1/C0)

Is it right ?

mpig

Added after 1 hours 48 minutes:

Dear hr_rezaee :

Do we need to care +/- sign of capacitor charge in the first and second circuit ?

mpig

 

[hr_rezaee]

Hi
I think there is a mistake in second S/H.
I think path from input to output is extra.
If we remove this path we have:

Sample phase :
Q0=Vin.C0, Q1=DAC.C1

Vout=Q0/C0=Vin

I'm not shure this circuit is true.
regards

 

[mpig09]

Dear hr_rezaee :

I use hspice to verify the gain result, Vout approaches 2*Vin - DAC*(C1/C0)
, I try to calculate this result, but the result is still not correct.

Could you have any suggest ?


mpig

 

[hr_rezaee]

Hi
could you attach an image that shows full circuit?
all switches and nodes.
regards

 

[mpig09]

Dear hr_rezaee :

I can't show detail schematic.
I hope it is enough to help.

mpig

 

[hr_rezaee]

Hi
Sorry
I can't Understand.
If you can, draw better schematic
Please explain where you see this S/H?
regards

 

[mpig09]

Dear hr_rezaee :

It is my project.

mpig

 

[hr_rezaee]

Hi
Ok, but you must have more detail about it.
such as type of S/H or references.
regards