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if you're using calibre tool for your verification you cannot parse or continue your lvs run unless you change your Calibre >Setup> LVS Option then untick Abort LVS on power/ground net errors.
if that's not the case and you have an LVS result. you can click on the Calibre RVE window under the Output Files>Extraction or ERC Files, you can click the coordinates and that will give you an idea where the shorted nets are.
Depends on size of the layout, there are different ways you can proceed with.
what is the level of the layout your are working on like Block, IP and Chip etc.
I know only using Calibre and the answers for each type as follows:
In Block level - This one is easy, once you have calbre run completed, start RVE from it, in RVE form you can find a short database in output files which is on left side. Once you open shorts database it will list out all the discrepancies which are related to all the shorts, we can just highlight all the errors related to vdd/vss then go to the layout and clearly look at the highlighted area where you can easily find out the short.
In IP-level - Try the above process and it may work out sometimes but if you are not then run the LVS using hierarchal option and then try the above process, if your are still not able too, then run the LVS using Hcell and Black box options and then try the above process.
In Chip level - this will take bit more time depends on the kind of short.
Run the LVS using Hierarchal and black box options, then open the shorts database from LVS RVE, in that just highlight the errors related to one metal and then start looking at the layout through the highlighted area, repeat this for every metal and you should be able to find the short.
I am sorry if this did not help or understood for you but
This is how I used to analyze and I could succeed.
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