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I try it in the pass time.
It's the must-be way to do in FPGA synthesis by DC.
Therefore I found most of the information reguard in insert_pad all
from Xilinx ftp/web. U can find it in their web.
BTW, I found many limit in doing auto insert pad .
U should follow this guid-line.
1. Name ur pad module interface signals in this rule
signal to/from pad begin with one prefix , for ex. pxxx and
avoid others signals from/to core begin with the prefix in the same
Then u can do the set_port_is_pad with the wildscard world p* .
2. U should check ur pad library first. U must follow its cell function and
pin polarity. for Ex. high or low active enable sensity. Otherwise DC
will translate by add one invert buffer or complaint the no suitable cell to map.
3. after insert_pad , try compile it. If u look the netlist that have the Gtech
Thanks again. I have read the script that you past. But I think it just for add pad in DC. I have done like that. DC always say that "P2A" is not usable, it have no function. I think because of our I/O library need to be config to meet our need. How can I do?