How to add IO during synthesis

[doreen105]

I have io lib,and the synthesis tool is RTL compiler of cadence.How to add IO to my design .When I import the gate netlist to encounter,will there a ring of IO around the core area???

Thanks very much

 

[sree205]

i don't know if i'm right or wrong. hopefully, ppl will correct me.

when i had a netlist, i opened the lib file to check for IO modules in it and used that to write a wrapper. i.e. for each input/output ports of my netlist, i made it pass through a io module in my lib.

the lef contains the physical information of the iopads. so, when netlist is imported to the backend tool, along with the io specification file, the pads get created.

 

[satyakumar]

Hi Sree205,
The procedure you said is corect, but it also need to add the location of the IO pad as a seperate constraint.

 

[deh_fuhrer]

i don't know if i'm right or wrong. hopefully, ppl will correct me.

when i had a netlist, i opened the lib file to check for IO modules in it and used that to write a wrapper. i.e. for each input/output ports of my netlist, i made it pass through a io module in my lib.

the lef contains the physical information of the iopads. so, when netlist is imported to the backend tool, along with the io specification file, the pads get created.

Hi Sree,
can you specify it more clearly..

 

[sarath51]

during synthesis only db are read actual IO are put during placement and foor planning

 

[deh_fuhrer]

during synthesis only db are read actual IO are put during placement and floor planning

what do you mean by "only db are read".....