How to achieve the flow from schematic to autolayout?

[smilodon]

Hi all,

My team will achieve a analog divider using analog method through cadence simulation. My question is who know the flow from schematic to achieve auto P&R? That is to say, schematic designer will give me a schematic, how can i achieve the layout using APR tool like Astro or Encounter from schematic? For the schematic is much huge, using custom layout will take much time.

Thanks!

 

[Adam.Yakuvitz]

Promoting an old topic by giving a first response to it . . .

Cadence has a series of products from the NeoLinear Acquisition called NeoCircuit and NeoCell that does the very same thing. It takes in a transistor level schematic netlist with specified W/L ratios and components such as caps and resistors and essentially generated a layout from it. I am not sure of how popular the product is but I know of a couple of companies who have invested in it.

I think this question may be more relevant in the Analog Circuit Design forum.

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ay

 

[deh_fuhrer]

laker have this tool....

 

[Adam.Yakuvitz]

laker? from silicon Canvas?
Do they have a product that takes transistor level schematic and converts into layout? Can you let me know the name of the product. I would be interested in experimenting with this. Is the Laker product stable?
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[beta1]

Analog circuit can't implemented by autolayout ( or Place and Route ) as digital circuit. There are some technique to speed upthe layout process such as using pcell, schematic drive layout (SDL) etc, fast auto place and route as Cadence IC Craftman . But basically you have to do by hand.

 

[Adam.Yakuvitz]

beta1,

The NeoCell product from Cadence Virtuoso is supposed to do what you said, which is why I answered the original question. NeoCell takes an analog cell schematic and with heavy constraints and guidance be able to translate into a physical synthesis. Call it auto-cell-synthesis and place and route for the analog domain. This tool really has'nt caught on because Analog designers need the flexibility for customization.

Correct me if I am wrong, but here's the datasheet.
https://www.cadence.com/datasheets/4922_VirtuosoNeoCell_DSfnl.pdf

Also let me know if you have gotten a chance to try out NeoCell, which to my understanding is integrated into Virtuoso platform as an add-on.
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ay

 

[okguy]

The main problem to use Neocell is the support from PDKs.
TSMC does not support it, and their Pcell are not compatible.
It flags an error when using it.

However, for an opamp, it takes 1hr to enter all the matching, well, guard-ring, crosstalk, wire width, power line characteristic (width, cell heigth, ...) ...
Then, analog P&R processing take again 1 hr.
So, it is a little faster than manual routing, using VXL and Pcell.

OkGuy