How to achieve the design frequency after synthesis

[imbichie]

Hi Friends

I am using Lattice ECP2 FPGA and for synthesis i am using ISPLever, now i am designing a system with 192Mhz. But after the Place and Route i cant achieve the 192 freq, it show only 97Mhz. so what are changes that i should make to achieve the 192Mhz after synthesis also.

Thanks in Advance

 

[permute]

with the information given:

fix it.


at a minimum, give a ratio. eg 95-5 route-logic, which might be a congestion or resource use issue (that might end up meeting your spec otherwise). or a 20-80 route-logic which would indicate a need for pipelining.

otherwise, the original "fix-it" remains. No info given = no info given back.

 

[anoop12]

Design may need architectural changes like pipeline and retiming. In Place and Route,
you may use timing driven PnR.