Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
According to me,
the calculation is right only when you are considering the transistors to be in saturation. That is both the Qs are in saturation, hence the voltage drop , Vce1, Vce2 are 0. So the value of Vb2 should be equal to or more than Vb2,sat.
if its convincing reply or else we can discuss more
the maximum permissible limit for current needs to be calculated.
you have current at the base of lower transistor. multiply it by beta of the transistor to get its emitter current..
if the upper transistor is in saturation, then it will be the maximum current flowing thoygh the circuit.
Added after 1 minutes:
the output of the circuit will be opposite of input to upper transistor and the output current to the external load will be the same you have calculated.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
