How the truth table functionality is implemented in LUTs?

[muni123]

Hi,

We know that CLB's comprises of slices and slices is made of LUT's, memory cells.

When we program an FPGA using bit file the required functionality is implemented in memory cells as truth table and that truth table is implemented in LUT.

Could anyone explain how the truth table functionality is implemented in the LUTs by taking an example.

Correct me if I'm wrong.

Thanks in advance!!!

 

[vipinlal]

Re: LUT in FPGA

I found a nice article here:
**broken link removed**

This is what I think(pls correct me if I am wrong):
A look up table is implemented by storing the all the output combinations in memory. For example a LUT-4 has 4 inputs so it can be used to design 16 different minterms.For each minterm a 16-bit memory is loaded with the logic bits. These bits are accessed, just like a RAM location is accessed.

 

[hafeez]

Re: LUT in FPGA

LUTs are used to store ur desired outputs, its kind of a RAM, now lets say if u have A truth table with 16 terms, means with 4 inputs and one output:

Here you can use a RAM (4x1), means with four address lines and one data line, to be exactly store all your truth table outputs. firstly using bit file these RAM (LUTs) are filled with ur truth table or min term outputs, now when ever the input condition appears on its address line (which is acting as input for ur logic) the output appears on Data line as desired by truth table variables!

dnt have any graphic files to explain

 

[Malek Lamari]

Re: LUT in FPGA

The LUT is filled with all possible outputs, and a multiplexer selects one of them based on the address given to him.
that is, the outputs are stored in a organized fashion that depends to the given combination of inputs.