May 27, 2007 #1 K khaila Full Member level 2 Joined Jan 13, 2007 Messages 121 Helped 5 Reputation 10 Reaction score 1 Trophy points 1,298 Activity points 2,105 Supposed we shall add a constant to STD_LOGIC_VECTOR: A_UNS : in std_logic_vector(3 downto 0); Y1_UNS : out std_logic_vector(3 downto 0); Y2_UNS : out std_logic_vector(3 downto 0); . . signal y_uns_std : std_logic_vector(3 downto 0); constant y_const : std_logic_vector(3 downto 0) := "1111"; . . y_uns_std <= "1111"; . . Y1_UNS <= A_UNS + y_uns_std ; Y2_UNS <= A_UNS + y_const ; . . HOW THESIZER will tret Y1_UNS and Y2_UNS ??? Is there any different???
Supposed we shall add a constant to STD_LOGIC_VECTOR: A_UNS : in std_logic_vector(3 downto 0); Y1_UNS : out std_logic_vector(3 downto 0); Y2_UNS : out std_logic_vector(3 downto 0); . . signal y_uns_std : std_logic_vector(3 downto 0); constant y_const : std_logic_vector(3 downto 0) := "1111"; . . y_uns_std <= "1111"; . . Y1_UNS <= A_UNS + y_uns_std ; Y2_UNS <= A_UNS + y_const ; . . HOW THESIZER will tret Y1_UNS and Y2_UNS ??? Is there any different???
May 28, 2007 #2 B bulx Full Member level 4 Joined Aug 7, 2004 Messages 223 Helped 47 Reputation 94 Reaction score 17 Trophy points 1,298 Activity points 1,520 yes, a good synthesiser would produce a much smaller circuit than a general prupose 4-bit adder -b
May 30, 2007 #3 A amitgvlsijune06 Junior Member level 2 Joined Mar 23, 2007 Messages 20 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,409 in the first case 1. signal = latch , + = half adder, out = wire so latch ,adder = wire out 2. input = wire , output = wire, half adder this will be the difference.its better yu synthesize and check as the signal might be taken as an FF too. thank you
in the first case 1. signal = latch , + = half adder, out = wire so latch ,adder = wire out 2. input = wire , output = wire, half adder this will be the difference.its better yu synthesize and check as the signal might be taken as an FF too. thank you