How the Ivdd varies when the devices get fast

[Sambhav_1]

Hi,

I working on technology node(deep submicron process) whose devices are fast as compared to the previous technology. I observed that ivdd has reduced 4 to 5 times with fast devices,however the cap has not reduced 4-5 times.How am i getting this much low numbers?

 

[deep_sea]

What is ivdd?

 

[Sambhav_1]

What is ivdd?

current from power supply

 

[dick_freebird]

There is more to dynamic Idd than simple
capacitance. None of the capacitances
except the wireload are simple.

The other main element besides gate
displacement current (fan-in load) is the
shot-through drain current of N and P
devices both "on" for a portion of the
rise, fall time intervals.

A "fast" device (medium or low VT) trades
increased static power for a better rise /
fall / delay time. A gate driven by a leisurely
transition spends more time cross-conducting.
Fast gates drive this element down, while
being no different in the switching load they
themselves present.

 

[Sambhav_1]

There is more to dynamic Idd than simple
capacitance. None of the capacitances
except the wireload are simple.

The other main element besides gate
displacement current (fan-in load) is the
shot-through drain current of N and P
devices both "on" for a portion of the
rise, fall time intervals.

A "fast" device (medium or low VT) trades
increased static power for a better rise /
fall / delay time. A gate driven by a leisurely
transition spends more time cross-conducting.
Fast gates drive this element down, while
being no different in the switching load they
themselves present.

my static power is also reduced

 

[Sambhav_1]

my static power is also reduced

any other reason?

 

[dick_freebird]

Of course there must be, but you would have
to provide more useful clues.

"Fast" devices should be leakier and raise the
static Idd. If this were not true then there would
be no value in the high / regular VT devices.

Of course if this is an analog question then
there are many more possibilities related to
circuit design. I'm assuming since you said
nothing specific about circuits, that this pertains
to digital logic.

If you looked into -where- the current flows
and -where- it changes, you might follow
that thread and end up at "why?".