somaja
Newbie level 1
axi interconnect
Hi,
I'm working on SOCC verification of RAID controller.I've PCIe Core- AXI Bridge on chip.The transactions initiated from PCIe core goes through the AXI Master to AXI Interconnect, to which multiple masters and slaves are connected.
In our design , PCIe Core can issue 8 outstanding read and writes.
But one of the slaves connected to the AXI Interconnect doesn't support the outstanding (No support for different AWID/WID's)
Are the outstanding transactions of PCIe Core would be stored in internal buffers and will be isssued one by one by the master?If so, is the responsibility of the AXI Interconnect to make the master to issue the bursts with single ID?Here the decoding will be done based on Address.
Can anyone please clarify on this?
Hi,
I'm working on SOCC verification of RAID controller.I've PCIe Core- AXI Bridge on chip.The transactions initiated from PCIe core goes through the AXI Master to AXI Interconnect, to which multiple masters and slaves are connected.
In our design , PCIe Core can issue 8 outstanding read and writes.
But one of the slaves connected to the AXI Interconnect doesn't support the outstanding (No support for different AWID/WID's)
Are the outstanding transactions of PCIe Core would be stored in internal buffers and will be isssued one by one by the master?If so, is the responsibility of the AXI Interconnect to make the master to issue the bursts with single ID?Here the decoding will be done based on Address.
Can anyone please clarify on this?