I can answer your question from an FPGA design standpoint.
FPGAs don't have inbuilt latches - Only FFs.
If you describe a latch in HDL, the synthesis tool will try to make do and emulate a latch behavior via a combinatorial loop (using the LUTs of the fabric).
Although in simulation you'll see the latch reacting in zero time - the real behavior of the circuit will have timing characteristics that are hard to predict and may vary strongly with temperature change.
But as I said, this is for FPGAs.
Hope someone can illuminate us more.