ncverilog +notimingchecks
Hi ,
Use ncverilog command line option , its a 3 step process (does compilation , elaboration & Simulation) . +notimingchecks speeds up the simulation process , but at the cost timing violation checks which is really required in a gate level simulation.
You can suppress the default generation of Log file by using +nolog as the option , can improve simulation speed.
Also check ur time precision in `timescale , if ur design is operating at very high speeds then go for high precision , other wise go for lower one .This really makes a great difference in simulaion speed & performance.
Hope u got some info ......