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How speedup NCverilog

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rlogin

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ncverilog command line option

Dear all,

I am using NC-verilog to simulate our design (about 3M gate).
For almost function-patterns, only a few stimulus are changed.
although when ncvlog phase,I separated library,gate and top
bench(includes stimulus), ncelab still costs a long time.

Can anyone tell me a way to speedup my simulation wth my
case.

Thanks
 

JesseKing

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speedup ncvrilog

Gate level sinulation is always a time consuming operation, you can use a formal check + STA methedology to overcome this problem.
But some guys are more familiar with the dynamic simulation and have no confidence STA.
 

rlogin

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ncverilog speed up

Thank you for reply.

In fact, just as you said, we are now using formal check(lec)+STA.
But gate simulation still needed in some cases.
(rtl simulation has the same question)

Here i just want to know is there some tips to speedup NCverilog.
I've tried +notimingcheck -access,etc, it really works, but the anxious
is TOO long time by elaboration not ncsim.
 

chandhramohan

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ncverilog +notimingchecks

Hi ,
Use ncverilog command line option , its a 3 step process (does compilation , elaboration & Simulation) . +notimingchecks speeds up the simulation process , but at the cost timing violation checks which is really required in a gate level simulation.
You can suppress the default generation of Log file by using +nolog as the option , can improve simulation speed.
Also check ur time precision in `timescale , if ur design is operating at very high speeds then go for high precision , other wise go for lower one .This really makes a great difference in simulaion speed & performance.

Hope u got some info ......
 

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