I think the basic misunderstanding is that the transistor HAS to go through the linear region to go to saturation, which I assume only stems from the usual Id-Vds graph, where the linear region is on the left of the graph. There is no physical reason why the transistor has to go through the linear region. Linear region means there is a channel all along the area between the source and the drain terminals (because the voltage difference between the gate and all points in that area is large enough to form a strongly inverted channel, i.e. larger than Vth roughly). If this voltage difference is not large enough closer to the drain, there is no strongly inverted channel there and the transistor is in saturation. All the saturation state depends on is the voltage difference between the gate and all the points in the substrate between the source and the drain. If you think about it, since the saturation corresponds to part of the area not beeing strongly inverted, physically is a state that occurs BEFORE the existence of a strongly inverted channel everywhere, i.e. the linear region.
Of course to call the transistor saturated you DO need a strongly inverted channel close to the source terminal. That's why (strong inversion) saturation doesn't occur for Vgs<Vth.