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constructing linear saturation states of PMOS netlist

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yefj

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Hello,I am using a Pmosfet with netlist from this
https://sanjayvidhyadharan.in/Downloads/tsmc_180_nm/tsmc018.lib
saturation is Vds>Vgs-V_th
linear is Vds>Vgs-V_th

Could you guide me with what exact plots to do in order t see the cutoff saturation linear regions?
Thanks.
1679429947852.png
 

Your "V1 list 0" should in fact be a list of gate voltages
that are 0 (cutoff), slightly below VT but on the slope
(subthreshold), well above VT (linear).

You might find it easier in total, to place multiple devices
with multiple Vgs, Vds forcing sources so you can plot
any / all from a single run. The schematic appears to be
LTSpice, you already have the models (one hopes) and
should be pretty simple to set up (if there isn't already a
LTSpice schematic (.asm?) in the bundle).
 

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