How simulation tool maps rtl code

[seeker_123]

Hi everyone
I am looking for how simulation tool(modelsim) and synthesis tool maps RTL code.
In this I am not getting much information on how modelsim maps rtl code. How simulation model works ...?
can anybody help me in this ..?
Here is example like

always @(posedge clk)
begin
  k2 <= k1;
  k1 <= k2;
end

so simulation model do something like this

if(clk == posedge)
{
  temp = k2;
  k2 = k1;
  k1 = temp;
}

can anyone explain me this point by providing some more example


thanks

 

[Miralipoor]

It is two FlipFlop that output of ones is input of another

 

[seeker_123]

It is two FlipFlop that output of ones is input of another

Thanks miralipoor

for this example I know.
I want to know some more example. so if you can provide then it will be helpful

Thanks

 

[Miralipoor]

You are welcome,

PROCESS
VARIABLE result : BIT;
BEGIN
wait until clk’event and clk=‘1’;
result := ‘0’;
for i in 0 to 6 loop
result := result XOR inp (i);
end loop;
outp <= result;
END PROCESS;

this code is combinational and output is bit-xor of input,
code reference **broken link removed**

 

[dave_59]

Verilog simulators follow the execution semantics defined by the LRM. Except for optimizations whose affects should not be visible to the user, a simulator does not care if the code it is executing is synthesizable RTL. The code in your example is interpreted as follows:

1. An always construct declares a concurrent process. It starts executing a statement or group of statements at time 0. When the all statements complete, it starts it all over again. The only difference between an initial and always construct is that an initial does not repeat.
2. The first statement has an event control that waits for a rising edge of clk. An event control is a blocking statement that suspends the process until event happens.
3. Once that wait is over, the process continues executing the begin/end statement.
4. A begin/end statement is a grouping of statements that execute serially. Each statement must complete before the next statement can execute. In your case, you have a set of assignment statements.
5. After the last assignment occurs, the block is finished and the always construct starts over again,

The non-blocking assignment statements (<=) have their own special execution semantics. The assignments are scheduled, but the actual update to the LHS variable does not occur until after everything at the current time is executed. They are called non-blocking because the next statement in the group of statements is allowed to execute before the assignment completes. In your example, and update to k1 is scheduled in the first assignment, but k1 has not been updated when the second non-blocking assignment begins its execution. So you get the old value of k1.

 

[seeker_123]

Thanks Dave
Its really helpful

simulator internally maps rtl code to some different way. Like I mention one example in my first post, for swapping two registers actually "temp" is nowhere but simulator tool may introduce some logic like this to mimic actual hardware(not visible to user). correct me if I am wrong.

like this example, can I have some more example in which i can get how simulator maps internally.

thanks

 

[dave_59]

Simulators do not need to map RTL code into hardware like synthesis tools do. It is software simulation of a hardware description language.

This is too complex a subject to discuss in a forum. You may want to read section 4 of the 1800-2012 LRM that discusses execution semantics. Also there are many on-line resources that discuss how non-blocking assignments work in Verilog.