How should I implent a Delay CELL in xilinx FPGA spatan6/

[wkong_zhu]

I want use delay chain to deglitch input signal. for example.
--------------------------------------
module ( input I, output O)
wire [9:0] delay_net; /* synthesis syn_keep = 1*/

BUF delaybuffer[9:0] ( .I({delay_net[8:0], I}), .O(delay_net[9:0]) );

assign O = delay_net[9];
endmodule
----------------------------------

But after synplify_pro synthesis, The BUFs disappeared totoally. only assign statements left.
How should I keep combinational Delays after Synthesis and APR.

Anybody help me.

- - - Updated - - -

I use LUT4 to act like a delay cell, It also failed.
the 'syn_keep' can only keep net name, it can not keep LUT.

 

[permute]

for synplify, you can use the syn_blackbox attribute. you may also need KEEP or S in the UCF file as well if MAP is set to do post-synthesis logic optimizations. You may also want to use FPGA editor to get LOC/DIRT constraints for the UCF. These are used to force MAP/PAR to use the exact same placement and routing.

 

[wkong_zhu]

Thanks, I will try syn_blackbox and KEEP.

After APR, xilinx generated verilog netlist with no hierarchy, It is not easy for me to find the delay cell.
How to generated hierarchical verilog netlist after APR??