Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Setup time is the minimum amount of time that the signal has to be held steady before the clock event, so the sampling will occur without problems.. You have to do a "sweep" in the time interval between the data signal (arriving), and the clock signal arrives.. the minimum amount of time between the data and clock that can put the output (Q) with the same value of D, is your Setup Time.
Hold time is the minimum amount of time that the data signal should be held after the clock event in order to be correctly sampled. Once again, you can sweep that difference in time, and check the minimum time.
Matematically, I think it is very hard to get those times.. you can try to do some "first order" analysis in your flip-flop to understand what stage is going to be critical for setup/hold time, but measuring it is going to be hard. But wait for someone else to awnser.
Above you can see is the timing diagram d flip-flop. It's relation between your CLK and input D. Normally, the value of tsetup and thold for d flip flop is given in the datasheet. Do you really need the calculation? In digital design, we normally calculate the setup time constraint and hold time constraint of our design.
common sharath666...... i know it is provided in db files with different combination of making d flipflop. it will be different for different d flipflop based on their internel design.... but how it is calculated????