How save the floating numbers in reg verilog?

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stackprogramer

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Hi, I define some reg variable when I initialize reg with integer, Everything is ok.

Code:
reg [15:0] a;
reg [15:0] b;
reg [15:0] c;
a=1;
b=2;

c=a*b;

When I want to initialize reg value with float I face with errors...
Code:
a=.005
b=-.004
c=a*b
Anyone can guide me? thanks in advance
 

Verilog is basically integer based, but to handle floats -



.https://primo.wiki/w3cnote/verilog2-real2int.html


Regards, Dana.
 
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