parasitic capacitance reduction in layout
The choice of ratio in the construction of high-frequency transistors (meander, etc.)Progress In Electromagnetics Research Symposium 2007, Prague, Czech Republic, August 27-30
A Study of Layout Strategies in RF CMOS Design
John Richard E. Hizon, Marc D. Rosales, Honee Lynn B. Tan
Maria Cecilia N. Gutierrez, Louis P. Alarcon, and Del¯n Jay Sabido IX
Microelectronics and Microprocessors Laboratory
Department of Electrical and Electronics Engineering
University of the Philippines, Diliman, Quezon City, Philippines
tech up to 12.5 * 0.18
well on the characteristics of 10 * 0.18