sudheer_vlsi
Junior Member level 2
Hi all,
I am designing 10 bit 100 MSPS DAC.on what basis i have to do segmentation? Theoritically,we can have some tradeoffs on power consumption,INL,DNL,Glitch and depending on that we will decide.it could be either 6+4 or 7+3.which one to take? are there any calculations for that?
plz send me if there are any papers for calculations?
I am designing 10 bit 100 MSPS DAC.on what basis i have to do segmentation? Theoritically,we can have some tradeoffs on power consumption,INL,DNL,Glitch and depending on that we will decide.it could be either 6+4 or 7+3.which one to take? are there any calculations for that?
plz send me if there are any papers for calculations?