how much margin should have?

[stormwolf]

Our project is a 100M soc , and process is 0.18, and how much timing margin should leave? thanks.

 

[semi_jl]

Hi,
The frequency 125M is OK, in my opinion.

 

[nitu]

Hi,
The frequency 125M is OK, in my opinion.

Can you please explain how do you arrive at this figure ?

 

[xiaoyoujun]

If your clk is 100M (10ns), based on tsmc or umc foundry, on 5% timing margin is available for your design(slow case). For tsmc/umc/ibm/charted foundry, their timing models are accurate based on their process. So 5% marging is enough.

 

[funster]

from my past experience.

setup margin can be 1ns,

hold time margin can be 0.2ns.


best regards

Our project is a 100M soc , and process is 0.18, and how much timing margin should leave? thanks.

 

[laglead]

Our project is a 100M soc , and process is 0.18, and how much timing margin should leave? thanks.

For setup time, you can use 120MHz. for hold time generally 0.2ns.