How much clock do I need for this for loop in Verilog?

[alangs]

for loop in verilog

how much clock is required for the below for loop...

always @ (posedge clk)begin
for(index = 0;index < 10;index = index + 1)begin
row1[index] <= #1 row2[index];
end
end

In simulation i see it is taking only clock....is it possible???

 

[FvM]

for loop in verilog

Iteration schemes in HDL are creating parallel logic rather than sequential action. Thus all iteration branches are assigned at the same clock edge respectively asynchronously, depending on the surrounding block.