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how minimize output voltgae spikes in sepic dc dc converter

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Maloth Ramesh

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when i implemented below in real time hardware circuit, i am getting output voltage spike during the switching instants can someone please help, Capture.PNG

and there is spike in switch current during the turn on period
 

BradtheRad

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Your D6/ C4/ R10 section resembles a snubber network as might be used to eliminate voltage spikes generated by inductor switch-off. Is that its purpose in your schematic? (Just an uninformed guess on my part.) Is it a correct arrangement?

Wires are shown in parallel to D1, but should there be a component as well?
 

FvM

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there is spike in switch current during the turn on period
Brought up by the R1/C4/D6 snubber dimensioning which doesn't look well considered. How did you arrive at the component values?
 

KlausST

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Hi,

adding an LC output filter will reduce the spikes.

Klaus
 

T

treez

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YOU GOT VERY BIG VALUE SEPIC CAP.....(sorry caps).....do you not find you seeing a big, very low frequency sinusoidal envelope to your input current?

uncoupled Sepic should best be designed as a flyback at first, but using inductors of half the value and obviosuly coupled as in flyback.....then you see your fet and diode currents are the same as what you will see in the uncoupled sepic...remember that the uncoupled sepic should be twice value you used for the flyback......best to make your sepic inductors the same value aswell, its easier. What is your vout?


...so first design a flyback (just use perfect flyback transformer coupling in your simulator) to do the job, then post it here and ill tell you how to adjust it for use with/as the uncoupled sepic.

remember your sepic cap only needs to be big enough to have less than 5% voltage ripple.
 

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Maloth Ramesh

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YOU GOT VERY BIG VALUE SEPIC CAP.....(sorry caps).....do you not find you seeing a big, very low frequency sinusoidal envelope to your input current?

uncoupled Sepic should best be designed as a flyback at first, but using inductors of half the value and obviosuly coupled as in flyback.....then you see your fet and diode currents are the same as what you will see in the uncoupled sepic...remember that the uncoupled sepic should be twice value you used for the flyback......best to make your sepic inductors the same value aswell, its easier. What is your vout?


...so first design a flyback (just use perfect flyback transformer coupling in your simulator) to do the job, then post it here and ill tell you how to adjust it for use with/as the uncoupled sepic.

remember your sepic cap only needs to be big enough to have less than 5% voltage ripple.

my out put voltage has to vary from (50-250)volts, by theoritical calculation i got cap value 220uF, but i used 470uF insted
 

T

treez

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if you do in ltspice and post here I can check your waveform for you.
The resonant frequency between youe sepic cap and two uncouple dinductaors is 164 hz...that is very very low....you cannot snub it out.....don't you see a ringing wave of that frequency when you start up , or after transient?...this would normally be a big problem with that big size of sepic cap....and would mean you need to go to coupled sepic instead.
 

Maloth Ramesh

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i don't know about resonance frequency between sepic cap and inductors. can you please give souce of information about it.i designed this converter based on information https://www.ti.com/lit/an/slyt309/slyt309.pdfhttp://www.ti.com/lit/an/slyt309/slyt309.pdf
actually i want to design a dc-dc converter my input voltage range(75-150)V and output voltage range(50-250)V, load can vary from (0-1500)watt. I have to do both buck and boost operation.
does this sepic converter good for this.I got know from this forum discussion that normal sepic converter not usefull. which type of converter helpfull for this type of application.

thank you for your reply i will be waiting for your reply

- - - Updated - - -

Your D6/ C4/ R10 section resembles a snubber network as might be used to eliminate voltage spikes generated by inductor switch-off. Is that its purpose in your schematic? (Just an uninformed guess on my part.) Is it a correct arrangement?

Wires are shown in parallel to D1, but should there be a component as well?

yes the purpose of D6/C4/R10 is eliminate spikes generated by inductor
 

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How big are the spikes? and where exactly are they? your electro's will have a fair bit of ESL so a film cap in parallel is advised to soak up the HF spikes, also a tight layout often helps, so that the loop area for the current to flow in after fet turn off is as small as possible...!

- - - Updated - - -

e.g. the loop formed by C1, D1, C2 should be as small as possible....!
 
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treez

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can you send the inductor current waveforms of your simulation on max load? I think you will see the low frequency envelope I speak of.
Actually I think youd be better off doing a full bridge converter for your application. Sepic needs a snubber over the sepic cap and it will be too big for your app...also, the sepic cap will be too big as its 1500w
 

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Don't forget in the sepic the current in the mosfet is ~ 2 x the input current (more for higher o/p currents) and similarly for the o/p diode and the o/p diode sees more volts than just the o/p volts (Vin + Vout approx) and the AC currents in the Sepic blocking cap are pretty high too...! so choose components carefully - sepics can work at high power but need careful layout and careful choice of turn on and turn off speeds for the mosfet(s)...!
 

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I believe the discussion is partly running on cross puprposes, e.g. discussing the problems of a coupled SEPIC although the present design is apparently uncoupled.

It would be helpful to see a waveform of the queried voltage (and current) spikes to know what we are talking about. As far as I see, the main reason get a (negative) output voltage spike in the present simulation circuit is D1 reverse recovery. It can be only handled by using a faster diode or slowing down U3 turn on, or an output filter, as already suggested.
 

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output voltage spike is not due to coupled or uncoupled, but to the ESR / ESL on the output cap...!

- - - Updated - - -

there is no suggestion from the poster that the o/p volt spikes are negative...

- - - Updated - - -

The spike in the switch current at turn on IS due to an imperfect o/p diode...
 

FvM

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there is no suggestion from the poster that the o/p volt spikes are negative...
True, there's no usefull information at all. But the simulation circuit has no ESL, just a (small) ESR. As far as I see, you don't manage to get a large positive current peak into the output capacitor in this circuit.
 

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the poster says "when implemented in hardware" so likely there is significant ESL/ESR in o/p electro....

- - - Updated - - -

as drawn in the 1st post the diode part of the RCD snubber will only make the turn off Vspike worse, RC snubber only recommended.
 

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the poster says "when implemented in hardware" so likely there is significant ESL/ESR in o/p electro....
I didn't notice. In this case capacitor ESL and other parasitics are most likely dominant. Thanks for clarifying.

Would appreciate a measured waveform so much more.
 

schmitt trigger

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Yes, waveforms are necessary.

And taken at least for a couple of operating points also.....between the DCM and CCM points.
 
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Maloth Ramesh

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here the both inductor currents,diode and switch currents Capture.PNG
 

KlausST

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Hi,

the current peak in the green line could be caused by the reverse recovery of the RHR30120. datasheets says 85ns.

All other signals and waveforms seem to be OK.

With a current ripple of about 20A you can expect a voltage ripple of about 20mV caused by the R of 1mOhms. (This is with zero ESR of C2! Expect a higher rippple voltage)
Additionally you get a voltage ripple of about 270mV by the capacitance of 470uF and the current pulse of 20A with about 6.5us in length. (If it fully is caught by C2)

As said before, to reduce voltage ripple in the output, I suggest an additional LC or at least RC filter.

Klaus
 

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