Brought up by the R1/C4/D6 snubber dimensioning which doesn't look well considered. How did you arrive at the component values?there is spike in switch current during the turn on period
YOU GOT VERY BIG VALUE SEPIC CAP.....(sorry caps).....do you not find you seeing a big, very low frequency sinusoidal envelope to your input current?
uncoupled Sepic should best be designed as a flyback at first, but using inductors of half the value and obviosuly coupled as in flyback.....then you see your fet and diode currents are the same as what you will see in the uncoupled sepic...remember that the uncoupled sepic should be twice value you used for the flyback......best to make your sepic inductors the same value aswell, its easier. What is your vout?
...so first design a flyback (just use perfect flyback transformer coupling in your simulator) to do the job, then post it here and ill tell you how to adjust it for use with/as the uncoupled sepic.
remember your sepic cap only needs to be big enough to have less than 5% voltage ripple.
Your D6/ C4/ R10 section resembles a snubber network as might be used to eliminate voltage spikes generated by inductor switch-off. Is that its purpose in your schematic? (Just an uninformed guess on my part.) Is it a correct arrangement?
Wires are shown in parallel to D1, but should there be a component as well?
True, there's no usefull information at all. But the simulation circuit has no ESL, just a (small) ESR. As far as I see, you don't manage to get a large positive current peak into the output capacitor in this circuit.there is no suggestion from the poster that the o/p volt spikes are negative...
I didn't notice. In this case capacitor ESL and other parasitics are most likely dominant. Thanks for clarifying.the poster says "when implemented in hardware" so likely there is significant ESL/ESR in o/p electro....