how large is N=40 in PLL?

[savithru]

adlsim+pll

hi all,

From the deansbook on pll I read that N-counter value is the parameter which has largest impact on the Phase noise of a pll. The smaller this value is better the phase noise should be, as N values multiplies the noise.

Now I am using N=40.. Can you pls tell me , how large is my N value. To what extent this value affects my phase noise?

Pls reply

Thanks & Regards
SavithRu

 

[Eugen_E]

The level of the phase noise will increase with 20 log N = 32dB.
N can be that large, especially if the VCO has low phase noise, like LC VCO.

If your reference signal has good phase noise performance and the VCO has poor phase noise performance (like RC VCO), it is recomended to have a large bandwidth, so the PLL can easily track the reference.

 

[eng_Semi]

This is not large at all

 

[salem_eng1]

I will give you a practical example
For 2.4GHz ZigBee
Integer-N divider N=480 to 495
Fractional-N divider N=90 for fr=25MHz

40 is not large at all

 

[savithru]

The level of the phase noise will increase with 20 log N = 32dB.
N can be that large, especially if the VCO has low phase noise, like LC VCO.

If your reference signal has good phase noise performance and the VCO has poor phase noise performance (like RC VCO), it is recomended to have a large bandwidth, so the PLL can easily track the reference.

Thanks you all for your kind reply.

If I have a refernce signal of 5MHz, and my VCO is very noisy( ring type), Can you pls suggest a numerical number for the bandwidth...

How about 200kHz?

pls reply.

Thanks & regards
SavithRu

 

[salem_eng1]

The level of the phase noise will increase with 20 log N = 32dB.
N can be that large, especially if the VCO has low phase noise, like LC VCO.

If your reference signal has good phase noise performance and the VCO has poor phase noise performance (like RC VCO), it is recomended to have a large bandwidth, so the PLL can easily track the reference.

Thanks you all for your kind reply.

If I have a refernce signal of 5MHz, and my VCO is very noisy( ring type), Can you pls suggest a numerical number for the bandwidth...

How about 200kHz?

pls reply.

Thanks & regards
SavithRu

I think choosing the loop bandwidth is depend on many factors one of them is the fref and the other is the lock time (settling time) the loop B.W must be smaller than the fref/10 as a rule of thumb for the loop stability also must be larger than 2/Tsw where Tsw is the settling time.

Example: For ur design fref=5MHz Loop B.W<500KHz also if settling time=200uSec B.W must be more then 2/200usec or B.W>10KHz

So this is the range of the B.W can be
10KHz< B.w <500KHz

u can choose any value in between. But it prefers to choose it in the middle i.e. 255KHz but there is another factor to choose the B.W which is the VCO phase noise. Because the total output phase noise depends on the VCO phase noise until the loop B.W here we need the B.W to be high as possible to decrease the total B.W. Also we need to decrease the B.W as possible to decrease the effect of the phase noise of the other blocks. But here the VCO noise is the dominant so we prefer to increase the B.W.

So I think choosing 200 KHz is good if it is OK with the settling time.

 

[m.ghafoori]

I have an idea that you use ADLSim which is a free software on Analog Devices web site. It gvies you a full simulation of the loop. It can be used only if you have a synthesizer from Analog Devices such as ADF series. If so, you can try different loop bandwith with various loop filter structures.