How Jumper insertion reduce Antenna Effect ??

[Sathishkrishna10]

Hi..

How the splitting of wires reduces Antenna Effect. I referred no. of docs. still i have more doubts in it. Am so confused with it.

1. In case of single long wire(M1) to gate,

Assume the charge accumulated in M1 is 3x

2. In case of splitting the wire to 3 parts(M1-M2-M1),

the charge accumulated by M1,M2,M2 equals to 3x or less ??? (bcoz these 3 metals will be connected after all metals etched)

What is the difference between both case ????

 

[erikl]

What is the difference between both case ????

Nothing, of course.

 

[Sathishkrishna10]

Hi Erikl.

if both are same, why we go for second one (jumper insertion) ??? how it works during ion imp/etch ??

 

[erikl]

how it works during ion imp/etch ??

It helps for the M1 etch of course, if via12 is close to the gate in question. For the M2 etch it wouldn't help, except the M2 wire is connected anyway to a junction (diode). If not, it wouldn't help at all.

In such case a normally off diode (reverse direction) should be connected close to the gate.

 

[dick_freebird]

You have to understand how "antenna" charging works. The
charge is picked up along the edges of the etched feature,
and imposed on anything connected to that slab. There is
no upward connection at that moment. You care about, at
any particular point, the layer being etched and what below
it, it connects to. Antenna rules properly include estimation
of the attached gate area and, you'd hope, comprehension
of attached junctions as well - every MOS S/D is in fact a
"free antenna diode" - although I've seen PDKs with no such
clue that simply dinged and dinged and dinged you for long
lines that were in fact perfectly well protected. But those
rules were entirely a fiction, built with no test chips or
reliability characterization ever performed.

When you "add a jumper", you have not added it -yet-,
as far as the process feature in question (M1, say). At M1
etch, you have only "subtracted" - the break in M1 that is
part of the "jumper" construct. So you have (say) 3 segments
of (say) 1/3 the periphery more or less. That 1/3 might get
you to pass the antenna rules check where the entire line
intact would fail.

And so, (you'd like to believe) the devices attached will
receive 1/3 the gate tunneling charge and less than 1/3 the
reliability degradation, and everything would be OK. If the
rules were well proven and rational and all that kind of good
thing.

 

[Sathishkrishna10]

during metallization wires will be left floating, so that it will be act as temporary capacitor and collects charges. while using jumper every metal in same connection left floating during each metal etching process and collects charges. the wires left floating until all metal layers are etched.

My question is
1. After all metal etching the wires will be connected and the charge accumulated on each metal will increase(which is enough to breakdown gate oxide) ??"

2. What happens to charge accumulated on Metal1 during Metal2 etching ??? will it be swept out ??? if yes, How ???


it will be good for me if u clear this to me. thank you

 

[erikl]

1. After all metal etching the wires will be connected and the charge accumulated on each metal will increase(which is enough to breakdown gate oxide) ??"

Not after all metal etching, but where vias connect the wires. The accumulated charge will be added, of course.

2. What happens to charge accumulated on Metal1 during Metal2 etching ??? will it be swept out ??? if yes, How ???

If M2 is connected to M1, the charges simply are added, s. above.

 

[dick_freebird]

There are multiple strips and cleans between M1 (say) etch,
and M2 dep. These will provide time and path to discharge
floating metal segments' charge.

You would have at least M1 PR strip, M1 post-etch clean,
ILD dep, Via1 PR, Via1 etch, Via1 clean before the first M2
dep. And, whe nM2 comes down, it is a chip-scale shorting
sheet which is certain to connect to the substrate or reverse
junction, somewhere, equalizing it all.