how jerk is produced in CMOS inverter ?

[the_pro]

hello...

can any one tell me, how "jerk" is produced at the output of CMOS inverter during transitions and voltage level exceeds the supply voltage level ?

thanks in advance ...

 

[keith1200rs]

Coupling of the input signal through the gate-drain capacitance.

Keith

 

[the_pro]

thanks for your response ...

One more thing that i want to know that ,
whenever, we increase the frequency of input signal, the power consumption increases.
is it because of jerk that become more dominant at fast transition ? or because of more cycles that leads to more transitions ?

 

[keith1200rs]

It is the energy wasted charging and discharging the capacitances in the logic.

http://large.stanford.edu/courses/2010/ph240/iyer2/

Keith