How is zero produced at the output of a LDO?

[liucheng311]

hello,everyone
i am considering the physical meaning of half plane zero,i learned that there will be a zero produced when there are two signal paths from input to output.
but there is also a zero at the output of a LDO which is produced by the ESR and output capacitor,i dont know how this zero is produced,could anyone explain it please?

 

[zorro]

Re: how is zero produced

Hi,

By LDO do you mean low drop-out regulator, right?
Think that an RC series branch acts lika a "short circuit" for some (complex) frequency s0 such that R+1/(s0*C)=0, i.e. s0=-1/(RC).
At that complex frequency the output is short circuited, so the output votage is 0 even if there is a nonzero input at that frequency.
Non necessarily a zero is produced by two paths that cancel (this is one possible origin, but non the only one).
Regards

Z