asic vs fpga
Coding for every FPGA architecture should be individually thought out in order to fit the structure of logic elements, flip-flops and routing available in that FPGA. Of course, you can just write generic HDL without any consideration for the above, but the quality of results will be drastically poorer. FPGA's are a lot more sensitive to coding style due to comparatively low amount of "building blocks" available to synthesis in comparison to ASIC (lut, FF, routing versus. 2,3,4,6 input AND,OR,XOR,MUX, full adder, half adder, multiple types of flops etc. available in ASIC libraries).