The phenomenon that occurs is as follows:
The most positive voltage at the gate repels holes that are below silicon dioxide in the substrate P. This leaves latent negative charges associated with the electrons in atoms linked material aceptante.Due that this voltage is increased electrons in the n + regions are attracted to the area beneath the gate, causing the region investment is made evident.
We recommend reading of Chapter 2 of Design of Analog CMOS Integrated Circuits by B. Razavi.