How important is gate current in analog design?

[bo_diggz]

I'm a graduate student embarking on research in the area of analog IC design. My potential topic involves deriving circuit solutions to the problems caused by gate current (direct tunneling) to analog circuits in deep submircon CMOS technologies.

I have a few questions to the designers out there. How often is analog design done in deep submicron CMOS technologies (65 nm, 90 nm) where gate current is significant? If it is done, do you avoid thin-oxide devices because of gate current? If so, do you use thick-oxide devices instead? Would analog circuit techniques to deal with problems caused by gate current be of any use to you?

Please let me know what you think. Thanks for your help.

 

[JoannesPaulus]

Gate leakage is just one problem of many in analog design (like parasitic capacitance, STI, WPE...) and there are already a lot of different techniques to cope with that. If I were you, I wouldn't focus on circuit techniques to deal with gate leakage (just add them as an appendix to a broader subject).

 

[bo_diggz]

Thanks for your reply. When you refer to there being a lot of techniques to cope with gate current, can you pleave provide me with some examples? I'm interested to know what is currently being done to minimize its negative effects on analog design.

This is just one research project possiblity that I'm considering. I just wasn't sure how current analog designers are dealing with direct tunneling. Thanks for your help.

 

[JoannesPaulus]

I cannot give you examples since the techniques I know are my company's (and you might think that this is already a good reason to do research on this!) but I can tell you that you could look at the deep sub-micron MOS transistor as a BJT and the gate current is equivalent to the base current. I hope this is enough to get you thinking...

 

[bo_diggz]

The reason I asked for some examples is because I haven't found any circuit techniques that deal with the effects of gate current on analog design in the literature. I've done a pretty exhaustive literature search, but there just aren't many papers out there that suggest coping techniques. Instead, I've found a lot paperes that just complain about the negative effects direct tunneling has on analog design, instead of suggeting circuit techniques to cope.

Anyways, thanks for the idea about comparing a deep submicron MOSFET to a BJT. This seems like a reasonable comparison to me.

Added after 41 minutes:

The reason I asked for some examples is because I haven't found any circuit techniques that deal with the effects of gate current on analog design in the literature. I've done a pretty exhaustive literature search, but there just aren't many papers out there that suggest coping techniques. Instead, I've found a lot paperes that just complain about the negative effects direct tunneling has on analog design, instead of suggeting circuit techniques to cope.

Anyways, thanks for the idea about comparing a deep submicron MOSFET to a BJT. This seems like a reasonable comparison to me.

 

[leo_o2]

One of technique is to cancel the current leakage of MOS gate. In principle, you can inject a same current as that was drained away by gate leakage.
Please try feedback loop with opamp to achieve it accurately.