[SOLVED] how "if" statement in eldo works?

[vaah]

Hello guys,

I want to use sort of special function in a subcircuit. Let assume we have a subcircuit as specified below

.subckt res X Y param: ro=10K
R1 X Y ro
if (((X)-V(Y))>=1) .param ro= 5K
endif

.ends

It gives two errors as,

+ Syntax error in expression IF ( ( V ( X )-V(Y ) ) > 1) .PARAM RO = 5K
+ Error: signe < or > expected at IF ( ( V ( X )-V(Y ) ) > 1)

I was expecting to see these errors bu I wonder how I can do that if I don't want to use a Verilog-A model?
I appreciate your help

 

[dick_freebird]

I don't know if you can make a subcircuit act on results
it has yet to generate. That's what V(node) means, to me
and likely the simulator would think V(node) is to be a
declared vector then, only it may be reserved.

Consider veriloga if eldo has such an integration (?).
Also consider that such a case statement may make
the simulation unsolvable, hyperabrupt change in
circuit state generally doesn't work out well. A
B source that used tanh() to swing between 10K
and 5K over an acceptably small (but nonzero) range
would be a much better (in terms of probability of
actually finishing) solution.

Or, macromodel it with a switch primitive and two
resistors, if you must go SPICE-only