How I2C stop condition is achieved after acknowledgement

[Richa Verma]

please help me out in understanding how STOP condition will occur after ACK arrives on SDA line.

After data transmission, ACK occupies SDA line for one clock pulse and data on SDA line, along with ACK, changes when clock is low.(as shown in fig below)

__ _ _ _ _ __ __
SCL __| |__| |__| |__| |__
____ ____ _ _ _ ___
SDA |__| |_ _ _ |_______|

STT < DATA > ACK STP

STT: START
STP: STOP

condition of start bit: SDA line changes from HIGH to LOW level when SCL is HIGH
condition of stop bit: SDA line changes from LOW to HIGH when SCL is HIGH
ACK : SDA at LOW level for one clock cycle(data changes when SCL is at LOW level)

Does SDA remain at LOW level till SCL becomes HIGH(as shown in fig), now SDA will change from LOW to HIGH to attain STOP condition. If so, then ACK will not be of one clock pulse width!

If SDA need not to be stretched till SCL becomes HIGH, then how STOP condition can be achieved?

Thanks in advance!

 

[sankar.m8]

Check this timing diagram...you will get some idea...

 

[Richa Verma]

Check this timing diagram...you will get some idea...View attachment 106180

Thanks Sankar!
This figure cleared my doubt.