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How i can reverse order bits in VHDL code?

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salahmuftah

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Hi all,

I have a vector A(31 downto 0)
how to do in VHDL in order to obtain A(0 downto 31)

Thank's
 

You can write a for loop:
Code:
process 
begin
for index 0 to 31 
loop
  ROLLED_A ( 31 - index ) <= A ( index ) ;
end loop ;
end process ;

Instead you can use the ROR or ROL operators.
 
Last edited:

Hi all,

I have a vector A(31 downto 0)
how to do in VHDL in order to obtain A(0 downto 31)

Thank's

You can write a for loop:
Code:
process 
begin
for index 0 to 31 
loop
  ROLLED_A ( 31 - index ) <= A ( index ) ;
end loop ;
end process ;

Instead you can use the ROR or ROL operators.
Just to clarify, you can use a for loop like shaiko suggests to reverse the value in the A(31 downto 0) vector, but you can't reverse the vector to A(0 to 31). The vector would have to be declared as A(0 to 31).
 

You can write a for loop:
Code:
process 
begin
for index 0 to 31 
loop
  ROLLED_A ( 31 - index ) <= A ( index ) ;
end loop ;
end process ;

Instead you can use the ROR or ROL operators.

Its even simpler than that:


Code VHDL - [expand]
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signal a : std_logic_vector(31 downto 0);
signal b : std_logic_vector(0 to 31);
 
...
 
b <= a;



Here, b(0) = a(31), b(1) = a(30) etc.
 

Its even simpler than that
Questions...
Code:
signal a : unsigned ( 31 downto 0 ) ;
signal b : unsigned ( 0 to 31 ) ;
signal x : unsigned ( 31 downto 0 ) ;
signal y : unsigned ( 0 to 31 ) ;

x <= a + b ;
y <= a + b ;
1. Will the numeric value of x and y be the same?
2. Will bit a(0) be added to bit b(0) ?
 

1. Will the numeric value of x and y be the same?

Yes.

2. Will bit a(0) be added to bit b(0) ?
No. Bit a(0) will be added to b(31).

The Numeric_std functions treat all numbers as (n downto m) without reversing the range. So in the case of a (0 to N) number, 0 will be treated as the MSB.
 
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    shaiko

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You can write a for loop:
Code:
process 
begin
for index 0 to 31 
loop
  ROLLED_A ( 31 - index ) <= A ( index ) ;
end loop ;
end process ;

Instead you can use the ROR or ROL operators.

Hi Shaiko,
May I have a question?
if you use "for" loop like in your code and then implement its in FPGA, what will happen?
what difference when I use the follow code in stead of yours?
Code:
ROLLED_A(0) <= A(31);
...
ROLLED_A(31) <= A(0);
 

The for loop is equipment to your example. But results in fewer instances of rsi.
 

if you use "for" loop like in your code and then implement its in FPGA, what will happen?
what difference when I use the follow code in stead of yours?

No difference.
VHDL
You should always keep in mind the red part.
You describe hardware - nothing more. Same as drawing a schematic circuit - but in code.
The richer the language - the more ways there're to tell the same story.
 

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