Hi All
In my design D is changing just before clock edge but there were no violation reported. I know it is because of massive hold violation because launch clock is coming early and capture clock is coming because of which data slippage is happening. Can anyone help me what exactly happening here. Also why can't it be setup violation?
1. Have you simulation run considering min corner or max corner SDFs?
2. Do you see the failures or mismatches during 0-delay sim on the same register you are talking about?