How G-NMOS ESD design method

[bicave]

Design ESD using G-NMOS method so simple. Just connect Gate of "big" NMOS to GND and Drain is connected to PIN.

But problem here is the size of NMOS? how to determine and simulation the strengthen of this ESD structure.

Appreciate material or advice, thanks.

 

[erikl]

If the NMOS model is good enough for an ESD transient analysis, just try and run an HBM or MM ESD event on a G-NMOS example. You'll see if it is good enough!

 

[elwin1881]

you can use MEDICI for simulation, as usual, we follow the fab's size(W,L,finger)

 

[mikersia]

Each technology generation has typical range of parameter Vesd/um or Iesd/um (HBM) for standard ESD clamps. Try to find an appropriate information in materials of ESD/EOS simposium for your technology node. Typically it is assumed that ggNMOS has Vesd/um < 10V/um (3...5), and this value is strongly depend on layout quality. Following to a Fab ESD guidelines typically provide >= 2KV HBM in standard case. A nonstandard case (multi supply voltage, multy domains, HV case) create additional problems, to solve which it is better to have a skilled designer.
Simulation is also teoretically possible, but hardly implementable with reasonable accuracy.