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how fix hod time in FPGA?

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Full Member level 4
Mar 23, 2006
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fpga hold time violation

When i run FPGA, I found some hold time violation.

how can fix them?



fpga timing problem fixing

ususally there are no holdtime problem in fpga design.
if it happens,it means that the clock of you design is
a totally failure. you have to redesign you clock.
in fact, there are special clock resources in fpga architecture such as dcm and dll in xilinx fpga,dll in altera fpga. salted designers usually try there best to use them to slove the clock problem in fpga.


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fpga yout


then how about setup time in FPGA?


setup hold time clock to out fpga

Hold is at highest priority then Setup. FPGA can not perform or fails to operate if HOLD violations remains in the design.
The Setup violations directly gives the best operating frequency of the FPGA (performance).
Setup violations are broadly classifies based on Synchronizes/gated logic Like. Clock gating default setup violations , and recovery for synchronises.
In detail setup can be fixed before / after Clock tree Synthesis and post-routing.
Mostly used methods :
- Use best placement of logic physically ( Timing driven placement, force placement, Netweight , good floor planning e.t.c)
- Upsize the cells driving long nets
- If possible use high speed cells in the logical path causing setup
- Reduce logical depths by deleting cascading buffers/ restructuring .
- Pin Swapping / cloning / buffering / moving etc.


how to fix fpga timing

quan228228 said:

then how about setup time in FPGA?

In FPGA design some reason can cause the setup problems. i think the first task is to find out what caused the problem through reads yout sta report. when you find it you can try to fix it as the following way.
1. too many logic levels, this is always caused by deep nested "if else" in hdl code,
or big adder tree with no pipelining,big comparator or some other arithmetic circuits synthesized into combinatorial logic.
when the logic levels increase the setuoptime increase, by certain degree,setup time problems comes up.
method to decrease logic leves is to use "case" to take instead of "if else".
add pipelining into big arithmetic circuits that may be synthesized into combinatorial logic.
2 long route delay or big fanout
long route delay can cause a big propagation delay on signal,this delay will be add up to setup time. when the place and route is not proper in fpga,this problems will come up.
method to combat this problem is that you can try to use the highest p&r level
items which can be chosed in ise tool menu,and you can choose timing driven ,one hot code of state machine in synthesis attribute and place attribute of your design tool,cancle resource share attribute.

if the tool cann't solve this problem with its high effort level,then you have to do something yourself to gain the desired performance of design. you alse can used high speed net to replace the long delay net through write UCF constraint in ucf editor. make proper location constraints.
another way to resolve long delay in net is that you can insert sevel ffs on that long delay net to divide it into sevels short ones.

big fanout can cause a long transition time on the signal edge ,the big transition time can be add to setup time too.
two method can be used to resolve this problem,the first one: you can use your tool to fix this problem automatically, you can restict the fanout number listed in the synthesis tool property menu. change it inti a much small one if you had find out that the setup problem is caused by large fanout. the second one :you can duplicate the ff whit have a big fanout. use two or more ffs two drive the signal that had been driven by a single ff before.

3. unproperly designed asynchronism circuits,it can bring in setup problems too ,
try your best to avoid asynchronism design ,if it cann't be avoid ,use proper synchronizer circuit to make robust transition betweent asynchronism clock domains

4 add input and output registers to your design to hold the input data into fpga and output data out of fpga,then pack these registers into iob to mimimum the input delay and output delay at the boundary of your fpga

5 some advance techs can be used to promote your design performance too,
such as multicycle ,latch and so on


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