Is it feasible to design an inverter chain in 180nm CMOS technology driving 1-2 pF load with propagation delay less than 50 psec?
I know the question is too specific. However, if there is anybbody who is working in 180nm CMOS technology rigourously, then it may be a question of experience to answer. Actually. I am designing an inverter chain to drive 1-2 pF load but the propagation delay is significantly larger. Please help.
I am in 90nm CMOS and I get min inverter driving min inverter delays of 60ps... Therefore a 1-2pF load with 50ps is no possible... Unless there is some amazing design I am not aware about.... Additionally, if you are making an inverter chain, I would say you will get 80ps plus in 180nm per inverter stage, therefore, if you have like 5 to 6 inverters buffering up to drive your 1p-2p load, it will be 80psX5or6...