And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?
And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?
Forf internal layers, I use .010" (.25mm) clearance over the pad size.
So if I use a .020pad on a .010" via drill, the clearance pad is .030.
This is what I use for a 1mm BGA, where the spacing is .040 on the pads, so a .030 matrix of pads still leaves .010 clearance valleys.
Now on a .5mm BGA, you'd have to use more than 4 layers, and use a blind and buried via setup, such that you don't create these blocked off areas. You'd most likely have to use a more expensive via process also, such as Laser vias, which are much smaller (.005").