How far do we need to pullback the internal planes in multi layer PCBs?

[Johnson]

In standard 4-layer PCB, and regarding the FAB limitation, how far we need to pullback the internal planes?
What about 10, and 16-layer boards?

Thank you,

 

[touringmike]

Re: Plane Pullback

There is no set rule for this.
Every Fab house will have their own preferred clearance.

I've used a minimum clearance of .025" from edge to plane.
Doesn't matter how many layers you're using.

As a general rule, the minimum pull back should be equal to the closest distance you can place a trace on any edge of the board.

 

[Johnson]

Re: Plane Pullback

And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?

 

[touringmike]

Re: Plane Pullback

And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?

Forf internal layers, I use .010" (.25mm) clearance over the pad size.
So if I use a .020pad on a .010" via drill, the clearance pad is .030.

This is what I use for a 1mm BGA, where the spacing is .040 on the pads, so a .030 matrix of pads still leaves .010 clearance valleys.

Now on a .5mm BGA, you'd have to use more than 4 layers, and use a blind and buried via setup, such that you don't create these blocked off areas. You'd most likely have to use a more expensive via process also, such as Laser vias, which are much smaller (.005").