Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

How far do we need to pullback the internal planes in multi layer PCBs?

Status
Not open for further replies.

Johnson

Advanced Member level 2
Joined
Oct 4, 2004
Messages
520
Helped
28
Reputation
56
Reaction score
7
Trophy points
1,298
Activity points
3,613
In standard 4-layer PCB, and regarding the FAB limitation, how far we need to pullback the internal planes?
What about 10, and 16-layer boards?

Thank you,
 

touringmike

Member level 4
Joined
Jul 19, 2005
Messages
68
Helped
12
Reputation
24
Reaction score
1
Trophy points
1,288
Location
U.S.A.
Activity points
1,884
Re: Plane Pullback

There is no set rule for this.
Every Fab house will have their own preferred clearance.

I've used a minimum clearance of .025" from edge to plane.
Doesn't matter how many layers you're using.

As a general rule, the minimum pull back should be equal to the closest distance you can place a trace on any edge of the board.
 

Johnson

Advanced Member level 2
Joined
Oct 4, 2004
Messages
520
Helped
28
Reputation
56
Reaction score
7
Trophy points
1,298
Activity points
3,613
Re: Plane Pullback

And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?
 

touringmike

Member level 4
Joined
Jul 19, 2005
Messages
68
Helped
12
Reputation
24
Reaction score
1
Trophy points
1,288
Location
U.S.A.
Activity points
1,884
Re: Plane Pullback

Johnson said:
And how much is the clearance of plane to via(and other PTH)? In AD's sample project, it was .5mm, which cause a lot of problem! It punch the plane and prevent accessing BGA inner row of pins! How can I fix it?

Forf internal layers, I use .010" (.25mm) clearance over the pad size.
So if I use a .020pad on a .010" via drill, the clearance pad is .030.

This is what I use for a 1mm BGA, where the spacing is .040 on the pads, so a .030 matrix of pads still leaves .010 clearance valleys.

Now on a .5mm BGA, you'd have to use more than 4 layers, and use a blind and buried via setup, such that you don't create these blocked off areas. You'd most likely have to use a more expensive via process also, such as Laser vias, which are much smaller (.005").
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top