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Limitation using FR4 as dielectric in PCBs

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engr_joni_ee

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Hi,

We need to design a board having maximum frequency of digital signals around 2 GHz. It will be multilayer board using Zynq Ultrascale device and other components. Can we still use FR4 in the PCBs ? Up to which frequency and bandwidth (a function of rise time) can we use FR4 ?
 

FR4 is generally used for 2.4 and 5 GHz WiFi transceivers and recent high speed digital interfaces like SATA and PCIe. Restrictions have to be evaluated according to trace length and PCB stackup details, e.g. with signal integrity tools.
 

Let me first get the concept of rise time, bandwidth, and firth harmonics in digital signal.

If the signal frequency is 2 GHz then the rise time according to 10%-90% approximation is calculated below.

Time period of 2 GHz signal is 0.5 nsec
Rise time = 0.5/10 nsec = 0.05 nsec

The Bandwidth = 0.35/Rise Time = 0.35/ 0.05 nsec = 7 Ghz

Is the Bandwidth calculated above is 5th harmonics ?

If the stack up is defined correctly, and the trace width is impedance control, then can we use FR4 as dielectric in the PCB having signal as describe above ?
 

There is a wide range of epoxy+fiberglass loss tangent parameters in materials classed as Fire-Retardent level 4 or FR4 and some are worse than others.

The effective dielectric constant also reduces with higher f.

 
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Is the Bandwidth calculated above (the) 5th harmonic ?

No. You compared T of a sine wave used for estimating pulse risetime, then divided by ten and converted back to a sine. This is incorrect.

If you wanted to compute the relative amplitude of the 5th harmonic of square wave V(1f)/V(5f)=5/1 so on a log scale the 5th harmonic of 2 GHz = 10 GHz will be 20log(1/5) ~ -14 dB.

This is not to be confused with 5GHz bands used for Wifi and Mobiles.
 
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The purpose of posting the question was to know the minimum rise time and max clock frequency of the digital signal for which we can design the PCB layout using FR4.

Regarding the relationship between rise time and the bandwidth.

It's true that in practice, we cannot have zero rise time in digital signals. The digital waveforms in practice can be modeled as trapezoidal waveform corresponds to an approximation that relates the rise time of a signal to its bandwidth as:

BW = 0.35/Rise Time

By this definition if the rise time is 0.05 nsec than then the approximated bandwidth is 7 GHz.

If the stack up in the PCB layout is correctly defined and impedance control then can we still use FR4 as dielectric in PCBs ?
 
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FR4 can be used but "Controllled Impedance" Manufacturing principle should be applied. So, the manufacturer should guarantee the impedances and others.
Design should be done by taking "high speed design rules" into account that is pretty critical and time consuming.
Because the timing is everything in high speed digital circuits therefore timing/delaying/reflection must be verified by some additional software packages such as Hyperlynx, Sigxplorer etc.
 

I am still wondering on the question posted in #7. "The minimum rise time and max clock frequency of the digital signal for which we can design the PCB layout using FR4. "
 

BW = 0.35/Rise Time

By this definition if the rise time is 0.05 nsec than then the approximated bandwidth is 7 GHz.

If the stack up in the PCB layout is correctly defined and impedance control then can we still use FR4 as dielectric in PCBs ?

At 1 GHz you must be looking for low loss tangent FR4 such as products made by GETEK.
At 7 GHz you need to consider ceramic, Teflon (ROGERS) There may be exceptions.
The dielectric constant loss tangent of insulation change over this band.
For controlled impedances , using std FR4 Dk=4.6 one rule of thumb is use trace width/gap to ground plane w/g = 1.8 Zo= 50 , w/g=1, Zo= 66 ohms, w/g=0.5 Zo=85 ohms. so very thin laminates help lower impedance with thin traces.

If you want to use logic at these frequencies, I assume you will be using Current Mode Logic (CML, PECL or ECL))

If you are trying to use 74LVC logic (3.6Vmax) at 3V it is guaranteed to be 23 ohms max at 24 mA with an output risetime limited by load capacitance and ringing dependent on source matching to Zo.
 
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